IBM researchers in conjunction with Paul W. K . Rothemund of the California Institute of Technology are working on a new technology that is will allow them to arrange DNA origami structures on surfaces that are compatible with current semiconductor manufacturing equipment capabilities.
This research is part of an ongoing effort to maintain Moore’s Law, which says that every two years the amount of transistors that can be placed on an integrated circuit doubles. For the past four decades this law, named for the co-founder of Intel, Gordon Moore, has held true.
Experts worry that the law may not be sustainable for long though, due to rising costs associated with semiconductor manufacturing equipment. The price tag attached to building a new chip plant is typically in the billions and gets dearer as the chips get smaller. By 2014 chips will be expected to have geometries under 22 nanometers in accordance with the law, but the high cost is expected to de-rail this trend and according to a report by iSuppli will result in, ‘altering the fundamental economics of the industry.’
Spike Narayan, a manager in the Science & Technology division of IBM Research said in a statement on Monday, “The cost involved in shrinking (chip) features to improve performance is a limiting factor in keeping pace with Moore’s Law and a concern across the semiconductor industry.”
The aim of this new method is that millions of carbon nanotubes will stick to the DNA molecules and form precise patterns that way. A forthcoming paper slated to appear in the September issue of Nature Nanotechnology, entitled “Placement and orientation of DNA nanostructures on lithographically patterned surfaces,” co-authored by IBM and Caltech scientists, posits that if all goes according to plan, a fiscally viable solution will be found to reach sub-22-nanometer lithography down to 6 nanometers.
IBM said in a statement, “The utility of this approach lies in the fact that the positioned DNA nanostructures can serve as scaffolds, or miniature circuit boards, for the precise assembly of components, such as carbon nanotubes, nanowires, and nanoparticles.” By combining current technology and self-assembly significant cost savings could be realized in what has historically been the most expensive phase of chip making, the company said.